41.8 KB · ⇊ 12 parts · ⤓ Micron 41.8 KB · ⤓ HTML 85.2 KB

layout: Wide · Narrow · Centered

top

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

• History

• Control registers in IBM 360/67

• M67 CR0

• M67 CR2

• M67 CR4

• M67 CR5

• M67 CR6

• M67 CR8

• M67 CR9

• M67 CR10

• M67 CR11

• M67 CR12

• M67 CR13

• M67 CR14

• Control registers in IBM S/390

• Control registers in IBM z/Architecture

• Control registers in Intel x86 series

• CR0

• CR1

• CR2

• CR3

• CR4

• CR5–7

• Additional Control registers in Intel x86-64 series

• EFER

• CR8

• XCR0 and XSS

• See also

• Notes

• References

• External links

The early CPU lacked dedicated control registers, and relied on a limited set of internal signals and flags.cite-ref-1[1] When IBM developed a paging versioncite-ref-2[note 1] of the System/360, they added 16 control registerscite-ref-footnotem67prelim-httpbitsaversorgpdfibm360model67c20-1647-0-system-360-model-67-time-sharing-system-preliminary-technical-summary-1966pdfpage25-25-26-control-registers-3-0[2]cite-ref-footnotem67-httpbitsaversorgpdfibm360functional-characteristicsga27-2719-2-360-67-funccharpdfpage16-16-table-4-control-registers-4-0[3] to the design for what became the 360/67. IBM did not provide control registers on other S/360 models, but made them a standard partcite-ref-footnotes-370-httpbitsaversorgpdfibm370princopsga22-7000-10-370-principles-of-operation-sep87pdfpage81-4-8-4-11-control-registers-5-0[4] of System/370, although with different register and bit assignments. As IBM added new features to the architecture, e.g., DAS, S/370-XA, S/370-ESA, ESA/390, they added additional fields to the control registers. With z/Architecture, IBM doubled the control register size to 64 bits.

On the 360/67, CR0 and CR2 are used by address translation, CR 4-6 contain miscellaneous flags including interrupt masks and Extended Control Mode,cite-ref-footnotem67-httpbitsaversorgpdfibm360functional-characteristicsga27-2719-2-360-67-funccharpdfpage16-16-table-4-control-registers-4-1[3] and CR 8-14cite-ref-footnotem67-httpbitsaversorgpdfibm360functional-characteristicsga27-2719-2-360-67-funccharpdfpage31-31-35-control-register-bit-assignments-for-sensing-6-0[5] contain the switch settings on the 2167 Configuration Unit.

Control Register 0 contains the address of the segment table for dynamic address translation.

Control register 2 is the Relocation exception address register.

CR4 is the extended mask register for channels 0-31. Each bit is the 1/0 channel mask for the corresponding channel.

CR5 is reserved for the extended mask register for channels 32–63. Each bit is the 1/0 channel mask for the corresponding channel.

CR6 contains two mode flags plus extensions to the PSW mask bits.

| Field | Bit | Description |

|---|---|---|

| 0 | 0 | Machine Check Mask Extension for Channe… |

| 1 | 1 | Machine Check Mask Extension for Channe… |

| 2-3 | | Reserved for channel controllers 2-3 |

| 4-7 | | Unassigned |

| 8 | 8 | Extended Control Mode |

| 9 | 9 | Configuration Control Bit |

| 10-23 | | Unassigned |

| 24-31 | | External interrupt masking |

| | 24 | Timer |

| | 25 | Interrupt Key |

| | 26 | Malfunction Alert - CPU 1 (Ext. Sig. 2) |

| | 27 | Malfunction Alert - CPU 2 (Ext. Sig. 3) |

| | 28 | Reserved (Ext. Sig. 4) |

| | 29 | Reserved (Ext. Sig. 5) |

| | 30 | External Interrupt - CPU 1, 2 (Ext. Sig… |

| | 31 | Reserved (Ext. Sig. 7) |

Control Register 8 contains the assignments of Processor Storage units 1–4 to central processing units (CPUs) and channel controllers (CCs).

| Bit | Description |

|---|---|

| 0 | Processor Storage Unit 1 to CPU 1 |

| 1 | Processor Storage Unit 1 to CPU 2 |

| 2-3 | Reserved for CPU 3-4 |

| 4 | Processor Storage Unit 1 to CC 0 |

| 5 | Processor Storage Unit 1 to CC 1 |

| 6-7 | Reserved for CC 3-4 |

| 8 | Processor Storage Unit 2 to CPU 1 |

| 9 | Processor Storage Unit 2 to CPU 2 |

| 10-11 | Reserved for CPU 3-4 |

| 12 | Processor Storage Unit 2 to CC 0 |

| 13 | Processor Storage Unit 2 to CC 1 |

| 14-15 | Reserved for CC 3-4 |

| 16 | Processor Storage Unit 3 to CPU 1 |

| 17 | Processor Storage Unit 3 to CPU 2 |

| 18-19 | Reserved for CPU 3-4 |

| 20 | Processor Storage Unit 3 to CC 0 |

| 21 | Processor Storage Unit 3 to CC 1 |

| 22-23 | Reserved for CC 3-4 |

| 24 | Processor Storage Unit 4 to CPU 1 |

| 25 | Processor Storage Unit 4 to CPU 2 |

| 26-27 | Reserved for CPU 3-4 |

| 28 | Processor Storage Unit 4 to CC 0 |

| 29 | Processor Storage Unit 4 to CC 1 |

| 30-31 | Reserved for CC 3-4 |

Control Register 9 contains the assignments of Processor Storage units 5–8 to central processing units (CPUs) and channel controllers (CCs).

| Bit | Description |

|---|---|

| 0 | Processor Storage Unit 5 to CPU 1 |

| 1 | Processor Storage Unit 5 to CPU 2 |

| 2-3 | Reserved for CPU 3-4 |

| 4 | Processor Storage Unit 5 to CC 0 |

| 5 | Processor Storage Unit 5 to CC 1 |

| 6-7 | Reserved for CC 3-4 |

| 8 | Processor Storage Unit 6 to CPU 66 |

| 9 | Processor Storage Unit 6 to CPU 2 |

| 10-11 | Reserved for CPU 3-4 |

| 12 | Processor Storage Unit 6 to CC 0 |

| 13 | Processor Storage Unit 6 to CC 1 |

| 14-15 | Reserved for CC 3-4 |

| 16 | Processor Storage Unit 7 to CPU 1 |

| 17 | Processor Storage Unit 7 to CPU 2 |

| 18-19 | Reserved for CPU 3-4 |

| 20 | Processor Storage Unit 7 to CC 0 |

| 21 | Processor Storage Unit 7 to CC 1 |

| 22-23 | Reserved for CC 3-4 |

| 24 | Processor Storage Unit 8 to CPU 1 |

| 25 | Processor Storage Unit 8 to CPU 2 |

| 26-27 | Reserved for CPU 3-4 |

| 28 | Processor Storage Unit 8 to CC 0 |

| 29 | Processor Storage Unit 8 to CC 1 |

| 30-31 | Reserved for CC 3-4 |

Control Register 10 contains the Processor storage address assignment codes.

| Bit | Starting Address Code for |

|---|---|

| 0-3 | Processor Storage Unit 1 |

| 4-7 | Processor Storage Unit 2 |

| 8-11 | Processor Storage Unit 3 |

| 12-15 | Processor Storage Unit 4 |

| 16-19 | Processor Storage Unit 5 |

| 20-23 | Processor Storage Unit 6 |

| 24-27 | Processor Storage Unit 7 |

| 28-31 | Processor Storage Unit 8 |

Control Register 11 contains channel controller (CC) assignments.

| Bit | Description |

|---|---|

| 0 | CC 0 available on CPU 1 |

| 1 | CC 0 available on CPU 2 |

| 2-3 | Reserved for CPUs 3-4 |

| 4 | CC 1 available on CPU 1 |

| 5 | CC 1 available on CPU 2 |

| 6-7 | Reserved for CPUs 3-4 |

| 8-15 | Unassigned |

| 16 | CPU 1 to only CC 0 |

| 17 | CPU 1 to only CC 1 |

| 18-19 | Reserved for CC 2-3 |

| 20 | CPU 2 to only CC 0 |

| 21 | CPU 2 to only CC 1 |

| 22-23 | Reserved for CC 2-3 |

| 24-31 | Unassigned |

CR12 contains I/O Control Unit Partitioning.

| Bit | I/O Control Unit | Interface |

|---|---|---|

| 0 | 1 | 1 |

| 1 | 1 | 2 |

| 2 | 2 | 1 |

| 3 | 2 | 2 |

| 4 | 3 | 1 |

| 5 | 3 | 2 |

| 6 | 4 | 1 |

| 7 | 4 | 2 |

| 8 | 5 | 1 |

| 9 | 5 | 2 |

| 10 | 6 | 1 |

| 11 | 6 | 2 |

| 12 | 7 | 1 |

| 13 | 7 | 2 |

| 14 | 8 | 1 |

| 15 | 8 | 2 |

| 16 | 9 | 1 |

| 17 | 9 | 2 |

| 18 | 10 | 1 |

| 19 | 10 | 2 |

| 20 | 11 | 1 |

| 21 | 11 | 2 |

| 22 | 12 | 1 |

| 23 | 12 | 2 |

| 24 | 13 | 1 |

| 25 | 13 | 2 |

| 26 | 14 | 1 |

| 27 | 14 | 2 |

| 28 | 15 | 1 |

| 29 | 15 | 2 |

| 30 | 16 | 1 |

| 31 | 16 | 2 |

CR13 contains I/O Control Unit Partitioning.

| Bit | I/O Control Unit | Interface |

|---|---|---|

| 0 | 17 | 1 |

| 1 | 17 | 2 |

| 2 | 18 | 1 |

| 3 | 18 | 2 |

| 4 | 19 | 1 |

| 5 | 19 | 2 |

| 6 | 20 | 1 |

| 7 | 20 | 2 |

| 8 | 21 | 1 |

| 9 | 21 | 2 |

| 10 | 22 | 1 |

| 11 | 22 | 2 |

| 12 | 23 | 1 |

| 13 | 23 | 2 |

| 14 | 24 | 1 |

| 15 | 24 | 2 |

| 16 | 25 | 1 |

| 17 | 25 | 2 |

| 18 | 26 | 1 |

| 19 | 26 | 2 |

| 20 | 27 | 1 |

| 21 | 27 | 2 |

| 22 | 28 | 1 |

| 23 | 28 | 2 |

| 24 | 29 | 1 |

| 25 | 29 | 2 |

| 26 | 30 | 1 |

| 27 | 30 | 2 |

| 28 | 31 | 1 |

| 29 | 31 | 2 |

| 30 | 32 | 1 |

| 31 | 32 | 2 |

CR14 contains indicators.

| Bit | Indicator |

|---|---|

| 0-27 | Unassigned |

| 22 | 2167 Power On |

| 23 | Unassigned |

| 24 | Direct Control, CPU 1 |

| 25 | Direct Control, CPU 2 |

| 26-27 | Unassigned |

| 28 | Prefix, CPU 1 |

| 29 | Prefix, CPU 2 |

| 30-31 | Unassigned |

The control registers of ESA/390cite-ref-footnotes-390-esa-7-0[6] on the IBM S/390 are an evolutionary enhancement to the control registers on the earlier ESA/370,cite-ref-footnotes-370-esa-8-0[7] S/370-XAcite-ref-footnotes-370-xa-9-0[8] and S/370cite-ref-footnotes-370-10-0[9] processors. For details on which fields are dependent on specific features, consult the Principles of Operation.cite-ref-footnotes-390-esa-httppublibzboulderibmcomepubspdfdz9ar008pdfpage116-4-6-4-10-control-registers-11-0[10]

| CR | bits | Field |

|---|---|---|

| 0 | 1 | SSM-suppression |

| 0 | 2 | TOD-clock-sync control |

| 0 | 3 | Low-address-protection control |

| 0 | 4 | Extraction-authority control |

| 0 | 5 | Secondary-space control |

| 0 | 6 | Fetch-protection-override control |

| 0 | 7 | Storage-protection-override control |

| 0 | 8-12 | Translation format |

| 0 | 13 | AFP-register control |

| 0 | 14 | Vector control |

| 0 | 15 | Address-space-function control |

| 0 | 16 | Malfunction-alert subclass mask |

| 0 | 17 | Emergency-signal subclass mask |

| 0 | 18 | External-call subclass mask |

| 0 | 19 | TOD-clock sync-check subclass mask |

| 0 | 20 | Clock-comparator subclass mask |

| 0 | 21 | CPU-timer subclass mask |

| 0 | 22 | Service-signal subclass mask |

| 0 | 24 | Set to 1 |

| 0 | 25 | Interrupt-key subclass mask |

| 0 | 26 | Set to 1 |

| 0 | 27 | ETR subclass mask |

| 0 | 28 | Program-call-fast |

| 0 | 29 | Crypto control |

| 1 | 0 | Primary space-switch-event control |

| 1 | 1-19 | Primary segment-table origin |

| 1 | 22 | Primary subspace-group control |

| 1 | 23 | Primary private-space control |

| 1 | 24 | Primary storage-alteration-event control |

| 1 | 25-31 | Primary segment-table length |

| 2 | 1-25 | Dispatchable-unit-control-table origin |

| 3 | 0-15 | PSW-key mask |

| 3 | 16-31 | Secondary ASN |

| 4 | 0-15 | Authorization index |

| 4 | 16-31 | Primary ASN |

| 5 | 0 | Subsystem-linkage control |

| 5 | 1-24 | Linkage-table origin |

| 5 | 25-31 | Linkage-table length |

| 5 | 1-25 | When the address-space-function control… |

| 6 | 0-7 | I/O-interruption subclass mask |

| 7 | 1-19 | Secondary segment-table origin |

| 7 | 22 | Secondary subspace-group control |

| 7 | 23 | Secondary private-space control |

| 7 | 24 | Secondary storage-alteration-event cont… |

| 7 | 25-31 | Secondary segment-table length |

| 8 | 0-15 | Extended authorization index |

| 8 | 16-31 | Monitor masks |

| 9 | 0 | Successful-branching-event mask |

| 9 | 1 | Instruction-fetching-event mask |

| 9 | 2 | Storage-alteration-event mask |

| 9 | 3 | GR-alteration-event mask |

| 9 | 4 | Store-using-real-address-event mask |

| 9 | 8 | Branch-address control |

| 9 | 10 | Storage-alteration-space control |

| 9 | 16-31 | PER general-register masks |

| 10 | 1-31 | PER starting address |

| 11 | 1-31 | PER ending address |

| 12 | 0 | Branch-trace control |

| 12 | 1-29 | Trace-entry address |

| 12 | 30 | ASN-trace control |

| 12 | 31 | Explicit-trace control |

| 13 | 0 | Home space-switch-event control |

| 13 | 1-19 | Home segment-table origin |

| 13 | 23 | Home private-space control |

| 13 | 24 | Home storage-alteration-event control |

| 13 | 25-31 | Home segment-table length |

| 14 | 0 | Set to 1 |

| 14 | 1 | Set to 1 |

| 14 | 2 | Extended-save-area control |

| 14 | 3 | Channel-report-pending subclass mask |

| 14 | 4 | Recovery subclass mask |

| 14 | 5 | Degradation subclass mask |

| 14 | 6 | External-damage subclass mask |

| 14 | 7 | Warning subclass mask |

| 14 | 10 | TOD-clock-control-override control |

| 14 | 12 | ASN-translation control |

| 14 | 13-31 | ASN-first-table origin |

| 15 | 1-28 | Linkage-stack-entry address |

The control registers of z/Architecturecite-ref-footnotez-architecture-12-0[11] are an evolutionary enhancement to the control registers of the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.cite-ref-footnotez-architecture-httpswwwvmibmcomlibraryother22783213pdfpage209-4-9-4-12-control-registers-13-0[12] Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

| CR | bits | Field |

|---|---|---|

| 0 | 8 | Transactional-execution control |

| 0 | 9 | Transactional-execution program-interru… |

| 0 | 10 | Clock-comparator sign control |

| 0 | 13 | Cryptography counter control |

| 0 | 14 | Processor-activity-instrumentation-exte… |

| 0 | 15 | Measurement-counter-extraction-authoriz… |

| 0 | 30 | Warning-track subclass mask |

| 0 | 32 | TRACE TOD-clock control |

| 0 | 33 | SSM-suppression |

| 0 | 34 | TOD-clock-sync control |

| 0 | 35 | Low-address-protection control |

| 0 | 36 | Extraction-authority control |

| 0 | 37 | Secondary-space control |

| 0 | 38 | Fetch-protection-override control |

| 0 | 39 | Storage-protection-override control |

| 0 | 40 | Enhanced-DAT-enablement control |

| 0 | 43 | Instruction-execution-protection-enable… |

| 0 | 44 | ASN-and-LX-reuse control |

| 0 | 45 | AFP-register control |

| 0 | 46 | Vector enablement control |

| 0 | 48 | Malfunction-alert subclass mask |

| 0 | 48 | Malfunction-alert subclass mask |

| 0 | 49 | Emergency-signal subclass mask |

| 0 | 50 | External-call subclass mask |

| 0 | 52 | Clock-comparator subclass mask |

| 0 | 53 | CPU-timer subclass mask |

| 0 | 54 | Service-signal subclass mask |

| 0 | 56 | Initialized to 1 |

| 0 | 57 | Interrupt-key subclass mask |

| 0 | 58 | Measurement-alert subclass mask |

| 0 | 59 | Timing-alert subclass mask |

| 0 | 61 | Crypto control |

| 1 | 0-51 | Primary Address-Space Control Element (… |

| 1 | 54 | Primary subspace-group control |

| 1 | 55 | Primary private-space control |

| 1 | 56 | Primary storage-alteration-event |

| 1 | 57 | Primary space-switch-event control |

| 1 | 58 | Primary real-space control |

| 1 | 60-61 | Primary designation-type control |

| 1 | 62-63 | Primary table length |

| 2 | 33-57 | Dispatchable-unit-control-table origin |

| 2 | 59 | Guarded-storage-facility enablement con… |

| 2 | 61 | Transaction diagnostic scope |

| 2 | 62-63 | Transaction diagnostic control |

| 3 | 0-31 | Secondary ASN-second-table-entry instan… |

| 3 | 32-47 | PSW-key mask |

| 3 | 48-63 | Secondary ASN |

| 4 | 0-31 | Primary ASN-second-table-entry instance… |

| 4 | 32-47 | Authorization index |

| 4 | 48-63 | Primary ASN |

| 5 | 33-57 | Primary-ASN-second-table-entry origin |

| 6 | 32-39 | I/O-interruption subclass mask |

| 7 | 0-51 | Secondary Address-Space Control Element… |

| 7 | 54 | Secondary subspace-group control |

| 7 | 55 | Secondary private-space control |

| 7 | 56 | Secondary storage-alteration-event cont… |

| 7 | 58 | Secondary real-space control |

| 7 | 60-61 | Secondary designation-type control |

| 7 | 62-63 | Secondary table length |

| 8 | 16-31 | Enhanced-monitor masks |

| 8 | 32-47 | Extended authorization index |

| 8 | 48-63 | Monitor masks |

| 9 | 32 | Successful-branching-event mask |

| 9 | 33 | Instruction-fetching-event mask |

| 9 | 34 | Storage-alteration-event mask |

| 9 | 35 | Storage-key-alteration-event mask |

| 9 | 36 | Store-using-real-address-event mask |

| 9 | 37 | Zero-address-detection-event mask |

| 9 | 38 | Transaction-end event mask |

| 9 | 39 | Instruction-fetching-nullification-even… |

| 9 | 40 | Branch-address control |

| 9 | 41 | PER-event-suppression control |

| 9 | 43 | Storage-alteration-space control |

| 10 | 0-63 | PER starting address |

| 11 | 0-63 | PER ending address |

| 12 | 0 | Branch-trace control |

| 12 | 1 | Mode-trace control |

| 12 | 2-61 | Trace-entry address |

| 12 | 62 | ASN-trace control |

| 12 | 63 | Explicit-trace control |

| 13 | 0-51 | Home Address-Space Control Element (ASC… |

| 13 | 55 | Home private-space control |

| 13 | 56 | Home storage-alteration-eventl |

| 13 | 57 | Home space-switch-event control |

| 13 | 58 | Secondary real-space control |

| 13 | 60-61 | Home designation-type control |

| 13 | 62-63 | Home table length |

| 14 | 32 | Set to 1 |

| 14 | 33 | Set to 1 |

| 14 | 34 | Extended save-area control (ESA/390-com… |

| 14 | 35 | Channel-report-pending subclass mask |

| 14 | 36 | Recovery subclass mask |

| 14 | 37 | Degradation subclass mask |

| 14 | 38 | External-damage subclass mask |

| 14 | 39 | Warning subclass mask |

| 14 | 42 | TOD-clock-control-override control |

| 14 | 44 | ASN-translation control |

| 14 | 45-63 | ASN-first-table origin |

| 15 | 0-60 | Linkage-stack-entry address |

The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor.

| Bit | Name | Full Name | Description |

|---|---|---|---|

| 0 | PE | Protected Mode Enable | If 1, system is in protected mode , els… |

| 1 | MP | Monitor co-processor | Controls interaction of WAIT/FWAIT inst… |

| 2 | EM | Emulation | If set, no x87 floating-point unit pres… |

| 3 | TS | Task switched | Allows saving x87 task context upon a t… |

| 4 | ET | Extension type | On the 386, it allowed to specify wheth… |

| 5 | NE | Numeric error | On the 486 and later, enable internal x… |

| 16 | WP | Write protect | When set, the CPU cannot write to read-… |

| 18 | AM | Alignment mask | Alignment check enabled if AM set, AC f… |

| 29 | NW | Not-write through | Globally enables/disable write-through… |

| 30 | CD | Cache disable | Globally enables/disable the memory cac… |

| 31 | PG | Paging | If 1, enable paging and use the § CR3 r… |

Reserved, the CPU will throw a #UD exception when trying to access it.

Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.

Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in CR4 is set, the lowest 12 bits are used for the process-context identifier (PCID).cite-ref-intel-vol3a1-15-0[14]

Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine-check exceptions.

| Bit | Name | Full Name |

|---|---|---|

| 0 | VME | Virtual 8086 Mode Extensions |

| 1 | PVI | Protected-mode Virtual Interrupts |

| 2 | TSD | Time Stamp Disable |

| 3 | DE | Debugging Extensions |

| 4 | PSE | Page Size Extension |

| 5 | PAE | Physical Address Extension |

| 6 | MCE | Machine Check Exception |

| 7 | PGE | Page Global Enabled |

| 8 | PCE | Performance-Monitoring Counter enable |

| 9 | OSFXSR | Operating system support for FXSAVE and… |

| 10 | OSXMMEXCPT | Operating System Support for Unmasked S… |

| 11 | UMIP | User-Mode Instruction Prevention |

| 12 | LA57 | 57-Bit Linear Addresses |

| 13 | VMXE | Virtual Machine Extensions Enable |

| 14 | SMXE | Safer Mode Extensions Enable |

| 15 | | (Reserved) |

| 16 | FSGSBASE | FSGSBASE Enable |

| 17 | PCIDE | PCID Enable |

| 18 | OSXSAVE | XSAVE and Processor Extended States Ena… |

| 19 | KL | Key Locker Enable |

| 20 | SMEP | Supervisor Mode Execution Protection En… |

| 21 | SMAP | Supervisor Mode Access Prevention Enable |

| 22 | PKE | Protection Key Enable |

| 23 | CET | Control-flow Enforcement Technology |

| 24 | PKS | Enable Protection Keys for Supervisor-M… |

| 25 | UINTR | User Interrupts Enable |

| 63-26 | — | (Reserved) |

| Bit | Description |

|---|---|

| 0 | If set, enables support for the virtual… |

| 1 | If set, enables support for the virtual… |

| 2 | If set, RDTSC instruction can only be e… |

| 3 | If set, enables debug register based br… |

| 4 | If set, enables 32-bit paging mode to u… |

| 5 | If set, changes page table layout to tr… |

| 6 | If set, enables machine check interrupt… |

| 7 | If set, address translations (PDE or PT… |

| 8 | If set, RDPMC can be executed at any pr… |

| 9 | If set, enables Streaming SIMD Extensio… |

| 10 | If set, enables unmasked SSE exceptions. |

| 11 | If set, the SGDT, SIDT, SLDT, SMSW and… |

| 12 | If set, enables 5-Level Paging. |

| 13 | see Intel VT-x x86 virtualization . |

| 14 | see Trusted Execution Technology (TXT) |

| 15 | — |

| 16 | If set, enables the instructions RDFSBA… |

| 17 | If set, enables process-context identif… |

| 19 | If set, enables the AES Key Locker inst… |

| 20 | If set, execution of code in a higher r… |

| 21 | If set, access of data in a higher ring… |

| 22 | See Intel 64 and IA-32 Architectures So… |

| 23 | If set, enables control-flow enforcemen… |

| 24 | If set, each supervisor-mode linear add… |

| 25 | If set, enables user-mode inter-process… |

| 63-26 | — |

cite-note-211. In early drafts of the Intel SGX specification, bit 15 of CR4 was named "CR4.SEE" and was described as an SGX enclave-instruction enable bit.cite-ref-19[18] Later revisions of this specification removed references to this bit.cite-ref-20[19]

Reserved, same case as CR1.

Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel as IA32_EFER. Its MSR number is 0xC0000080.

| Bit | Purpose |

|---|---|

| 0 | SCE (System Call Extensions) |

| 1 | DPE (AMD K6 only: Data Prefetch Enable) |

| 2 | SEWBED (AMD K6 only: Speculative EWBE#… |

| 3 | GEWBED (AMD K6 only: Global EWBE# Disab… |

| 4 | L2D (AMD K6 only: L2 Cache Disable) |

| 5-7 | Reserved, Read as Zero |

| 8 | LME (Long Mode Enable) |

| 9 | Reserved |

| 10 | LMA (Long Mode Active) |

| 11 | NXE ( No-Execute Enable) |

| 12 | SVME ( Secure Virtual Machine Enable) |

| 13 | LMSLE (Long Mode Segment Limit Enable) |

| 14 | FFXSR (Fast FXSAVE/FXRSTOR) |

| 15 | TCE (Translation Cache Extension) |

| 16 | Reserved |

| 17 | MCOMMIT (MCOMMIT instruction enable) |

| 18 | INTWB (Interruptible WBINVD/WBNOINVD en… |

| 19 | Reserved |

| 20 | UAIE (Upper Address Ignore Enable) |

| 21 | AIBRSE (Automatic IBRS Enable) |

| 22–63 | Reserved |

CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).cite-ref-amd64-vol2-16-1[15]

The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros.

System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.

The TPR is cleared to 0 on reset.

XCR0, or Extended Control Register 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be changed using the privileged XSETBV read using the unprivileged XGETBV instructions.cite-ref-24[22]

| Bit | Name | Enabled Feature | Purpose |

|---|---|---|---|

| 0 | X87 | x87 FPU | x87 FPU/MMX State, must be '1' |

| 1 | SSE | SSE | MXCSR and 16 XMM registers |

| 2 | AVX | AVX | 16 upper-halves of the YMM registers |

| 3 | BNDREG | MPX | Four BND registers |

| 4 | BNDCSR | MPX | BNDCFGU and BNDSTATUS registers |

| 5 | OPMASK | AVX-512 | Eight k-mask registers |

| 6 | ZMM_Hi256 | AVX-512 | 16 upper-halves of the ZMM registers |

| 7 | Hi16_ZMM | AVX-512 | 16 "high" ZMM registers (ZMM16 through… |

| 8 | PT | Processor Trace | |

| 9 | PKRU | Protection Keys | PKRU register |

| 10 | PASID | | |

| 11 | CET_U | Intel CET | User shadow stack |

| 12 | CET_S | Intel CET | Supervisor shadow stack |

| 13 | HDC | Hardware Duty Cycling | |

| 14 | UINTR | User interrupts | |

| 15 | LBR | Last Branch Records | |

| 16 | HWP | Hardware P-states | |

| 17 | XTILECFG | Intel AMX | 64-byte TILECFG register |

| 18 | XTILEDATA | Intel AMX | Eight 1024-byte TILE registers |

| 19 | APX | Intel APX | 16 "high" GPRs (R16 through R31) |

| 20–63 | Reserved | | |

cite-note-252. The lower 128 bits of all YMM registers is stored in the SSE state.

cite-note-263. The lower 256 bits of ZMM registers ZMM0 through ZMM15 are stored in the SSE and AVX states.

cite-note-274. Even though Intel APX is indicated through bit 19 of XCR0, it is actually written, through XSAVE (the uncompacted form), in the unused 128 byte space left where Intel MPX went.

There is also the IA32_XSS MSR, which is located at address DA0h. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions.

| Bit | Purpose |

|---|---|

| 0–7 | Reserved; must be 0. |

| 8 | PT (Enables the saving and loading of n… |

| 10 | Processor Address Space ID (PASID) state |

| 11 | Control-flow Enforcement Technology (CE… |

| 12 | Control-flow Enforcement Technology (CE… |

| 13 | HDC (Enables the saving and loading of… |

| 14 | User interrupts (UINTR) state |

| 15 | Last branch recording (LBR) state |

| 16 | HWP (enables the saving/loading of IA32… |

| 17–63 | Reserved; must be 0. |

• General-purpose register

• Test register

• Model-specific register

• Debug register

• Flag byte

• Status register

cite-note-2note 1. ↑ IBM never shipped the 360/64 or 360/66, only the 360/67.

M67prelim citerefm67prelimSystem/360 Model 67 - Time Sharing System - Preliminary Technical Summary (PDF). Systems Reference Library (First ed.). IBM. C20-1647-0. Retrieved May 8, 2023. M67 citerefm67IBM System/360 Model 67 - Functional Characteristics (PDF). Systems Reference Library (Third ed.). IBM. February 1972. A27-2719-0. Retrieved May 8, 2023. S/370 citerefs-370IBM System/370 - Principles of Operation (PDF) (Eleventh ed.). IBM. September 1987. GA22-7000-10. Retrieved May 8, 2023. S/370-XA citerefs-370-xaIBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1. Retrieved May 8, 2023. S/370-ESA

citerefs-370-esaIBM Enterprise Systems Architecture/370 Principles of Operation (PDF) (First ed.). IBM. August 1988. SA22-7200-0. Retrieved May 8, 2023. S/390-ESA citerefs-390-esaIBM Enterprise Systems Architecture/390 Principles of Operation (PDF) (Ninth ed.). IBM. June 2003. SA22-7201-08. Retrieved May 8, 2023. z/Architecture citerefz-architecturez/Architecture - Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. SA22-7832-13. Retrieved May 8, 2023.

cite-note-11. ↑ "lab4.pdf" (PDF). Uppsala University. March 17, 2024. Archived (PDF) from the original on January 17, 2021. Retrieved March 16, 2024.

cite-note-footnotem67prelim-httpbitsaversorgpdfibm360model67c20-1647-0-system-360-model-67-time-sharing-system-preliminary-technical-summary-1966pdfpage25-25-26-control-registers-32. ↑ M67prelim, pp. 25-26, Control Registers.

cite-note-footnotem67-httpbitsaversorgpdfibm360functional-characteristicsga27-2719-2-360-67-funccharpdfpage16-16-table-4-control-registers-43. ↑ M67, p. 16, Table 4. Control Registers.

cite-note-footnotes-370-httpbitsaversorgpdfibm370princopsga22-7000-10-370-principles-of-operation-sep87pdfpage81-4-8-4-11-control-registers-54. ↑ S/370, pp. 4-8-4-11 , Control Registers.

cite-note-footnotem67-httpbitsaversorgpdfibm360functional-characteristicsga27-2719-2-360-67-funccharpdfpage31-31-35-control-register-bit-assignments-for-sensing-65. ↑ M67, pp. 31-35, Control Register Bit Assignments for Sensing.

cite-note-footnotes-390-esa-76. ↑ S/390-ESA.

cite-note-footnotes-370-esa-87. ↑ S/370-ESA.

cite-note-footnotes-370-xa-98. ↑ S/370-XA.

cite-note-footnotes-370-109. ↑ S/370.

cite-note-footnotes-390-esa-httppublibzboulderibmcomepubspdfdz9ar008pdfpage116-4-6-4-10-control-registers-1110. ↑ S/390-ESA, pp. 4-6-4-10, Control Registers.

cite-note-footnotez-architecture-1211. ↑ z/Architecture.

cite-note-footnotez-architecture-httpswwwvmibmcomlibraryother22783213pdfpage209-4-9-4-12-control-registers-1312. ↑ z/Architecture, pp. 4-9–4-12, Control Registers.

cite-note-145. Intel486 Microprocessor Family Programmer's Reference Manual (PDF). Intel. 1992. p. 4-7.

cite-note-intel-vol3a1-1514. ↑ citerefintel-corporation2016Intel Corporation (2016). "4.10.1 Process-Context Identifiers (PCIDs)". Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 3A: System Programming Guide, Part 1.

cite-note-amd64-vol2-1615. "AMD64 Architecture Programmer's Manual Volume 2: System Programming" (PDF). AMD. September 2012. pp. 127 & 130. Retrieved 2017-08-04.

cite-note-intel-5lp-176. "5-Level Paging and 5-Level EPT" (PDF). Intel. May 2017. p. 16. Retrieved 2018-01-23.

cite-note-intel-3a-187. "Intel 64 and IA-32 Architectures Software Developer's Manual" (PDF). Intel® Corporation. 2021-06-28. Retrieved 2021-09-21.

cite-note-1918. ↑ Intel, Software Guard Extensions Programming Reference, ref no. 329298-001, sep 2013 - chapters 1.7 and 6.5.2 describe CR4.SEE.

cite-note-2019. ↑ Intel, Software Guard Extensions Programming Reference, ref no. 329298-002, oct 2014 - makes no mention of CR4.SEE.

cite-note-228. citereffischer2011Fischer, Stephen (2011-09-21). "Supervisor Mode Execution Protection" (PDF). NSA Trusted Computing Conference 2011. National Conference Services, Inc. Archived from the original (PDF) on 2016-08-03. Retrieved 2017-08-04.

cite-note-239. citerefanvin2012Anvin, H. Peter (2012-09-21). "x86: Supervisor Mode Access Prevention". LWN.net. Retrieved 2017-08-04.

cite-note-2422. ↑ "Chapter 13, Managing State Using The Xsave Feature Set" (PDF). Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture. Intel Corporation (2019). Retrieved 23 March 2019.

Wikibooks has a book on the topic of:

X86 Assembly/Protected Mode

• Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3A

• Intel 64 and IA-32 Architectures Software Developer Manuals

• Tech Docs: AMD64

• Wyatt's World: Cracking Open the Pentium III (1999-05-28)